Concurrency 기초 — Concurrency vs Parallelism·Race·Memory Model

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int counter = 0;
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void task1(void) { counter++; }   // RMW: read, add 1, write
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void task2(void) { counter++; }

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Thread 1            Thread 2          counter
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read 0
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                    read 0
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add → 1
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                    add → 1
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write 1
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                    write 1            ← 1 (잘못! 2여야)

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#include <stdatomic.h>
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atomic_int counter = 0;
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atomic_fetch_add(&counter, 1);   // 원자적

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; ARM atomic add
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1: ldrex r0, [r1]
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   add r0, r0, #1
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   strex r2, r0, [r1]
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   cbnz r2, 1b   ; STREX 실패 (다른 thread가 끼어듦) → retry

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/* Thread 1 */
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x = 1;
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y = 1;
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/* Thread 2 */
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if (y == 1)
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    assert(x == 1);   // ← 항상 참? OoO·cache 때문에 *아닐 수 있음*

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ARMv7/v8: weakly ordered
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  Load → Load: 재정렬 OK
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  Load → Store: 재정렬 OK
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  Store → Load: 재정렬 OK
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  Store → Store: 재정렬 OK

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__DMB();   // 이전 access 모두 완료 보장

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atomic_store_explicit(&x, 1, memory_order_release);
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int v = atomic_load_explicit(&y, memory_order_acquire);

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/* Producer */
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data = 42;
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atomic_store_explicit(&ready, 1, memory_order_release);
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/* Consumer */
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if (atomic_load_explicit(&ready, memory_order_acquire) == 1) {
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    use(data);   // ← data = 42 보장
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}

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/* Thread 1 */
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x.store(1, seq_cst);
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r1 = y.load(seq_cst);
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/* Thread 2 */
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y.store(1, seq_cst);
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r2 = x.load(seq_cst);
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/* seq_cst: r1==0 && r2==0 *불가* */
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/* acq_rel: r1==0 && r2==0 *가능* — 양쪽 store가 다른 thread에 *다른 순서*로 보임 */

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ARM: seq_cst store → DMB ISH 명령 추가 (~30 cycle)
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     release store → 더 가벼움 (~5 cycle)
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Linux kernel — 대부분 release/acquire 사용.

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__DMB();   // Data Memory Barrier — memory access ordering
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__DSB();   // Data Sync Barrier — *모든* access *완료*까지 대기
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__ISB();   // Instruction Sync Barrier — pipeline flush, instruction refetch

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xSemaphoreTake(mtx, ...);
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queue.push(item);
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xSemaphoreGive(mtx);

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/* SPSC (single-producer single-consumer) queue */
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atomic_size_t head, tail;
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bool push(T item) {
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    size_t h = atomic_load_explicit(&head, memory_order_relaxed);
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    size_t t = atomic_load_explicit(&tail, memory_order_acquire);
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    if (h - t == CAPACITY) return false;
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    buf[h % CAPACITY] = item;
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    atomic_store_explicit(&head, h + 1, memory_order_release);
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    return true;
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}

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struct {
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    atomic_int a;   // CPU 0 사용
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    atomic_int b;   // CPU 1 사용
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} stats;

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/* Lock-free stack */
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T* top;
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pop():
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    T* old = top;            // read top = X
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    /* preempt — 누군가 X pop, Y push, X 다시 push */
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    /* top = X 다시 (그러나 next 다름) */
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    cas(&top, old, old->next);  // ← 성공! 그러나 잘못된 next

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volatile int counter;
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counter++;   // ← 여전히 RMW, atomic 아님

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atomic_store(&flag, 1);    // default seq_cst → 비쌈
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atomic_load(&flag);         // seq_cst → barrier

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Race가 1M 중 1회 발생 → 1 day in production → bug