UART 드라이버 구현 — polling·interrupt·DMA 3가지 방식 비교

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USARTDIV = f_pclk / (8 × (2 - OVER8) × baud)
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OVER8 = 0 (16x oversample, default) → USARTDIV = f_pclk / (16 × baud)
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예) PCLK1 = 42 MHz, baud = 115200
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    USARTDIV = 42000000 / (16 × 115200) ≈ 22.7864
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    Mantissa = 22 = 0x16
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    Fraction = round(0.7864 × 16) = 13 = 0xD
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    BRR = (0x16 << 4) | 0xD = 0x16D

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void uart_init_polling(uint32_t baud, uint32_t pclk) {
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    RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
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    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
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    // PA9 TX, PA10 RX (AF7)
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    gpio_init(GPIOA, 9,  &(gpio_config_t){.mode=GPIO_MODE_AF, .speed=GPIO_SPEED_HIGH, .af=7});
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    gpio_init(GPIOA, 10, &(gpio_config_t){.mode=GPIO_MODE_AF, .pull=GPIO_PULL_UP,     .af=7});
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    USART1->BRR = (pclk + baud / 2) / baud;   // round
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    USART1->CR1 = USART_CR1_UE | USART_CR1_TE | USART_CR1_RE;
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}
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void uart_putc(char c) {
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    while (!(USART1->SR & USART_SR_TXE));   // wait TX buffer empty
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    USART1->DR = c;
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}
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int uart_getc(void) {
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    while (!(USART1->SR & USART_SR_RXNE));  // block until RX
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    return USART1->DR;
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}
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void uart_puts(const char *s) {
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    while (*s) uart_putc(*s++);
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}

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#define RX_BUF_SIZE 256
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#define TX_BUF_SIZE 256
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static volatile uint8_t rx_buf[RX_BUF_SIZE];
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static volatile uint16_t rx_head, rx_tail;
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static volatile uint8_t tx_buf[TX_BUF_SIZE];
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static volatile uint16_t tx_head, tx_tail;
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void uart_init_int(uint32_t baud, uint32_t pclk) {
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    // ... GPIO + clock 동일
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    USART1->BRR = (pclk + baud / 2) / baud;
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    USART1->CR1 = USART_CR1_UE | USART_CR1_TE | USART_CR1_RE
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                | USART_CR1_RXNEIE;
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    NVIC_SetPriority(USART1_IRQn, 8);
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    NVIC_EnableIRQ(USART1_IRQn);
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}
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void USART1_IRQHandler(void) {
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    uint32_t sr = USART1->SR;
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    // RX
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    if (sr & USART_SR_RXNE) {
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        uint8_t c = USART1->DR;
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        uint16_t next = (rx_head + 1) % RX_BUF_SIZE;
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        if (next != rx_tail) {
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            rx_buf[rx_head] = c;
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            rx_head = next;
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        }   // else overflow — drop
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    }
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    // TX
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    if ((sr & USART_SR_TXE) && (USART1->CR1 & USART_CR1_TXEIE)) {
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        if (tx_tail != tx_head) {
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            USART1->DR = tx_buf[tx_tail];
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            tx_tail = (tx_tail + 1) % TX_BUF_SIZE;
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        } else {
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            USART1->CR1 &= ~USART_CR1_TXEIE;   // empty — disable
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        }
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    }
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}
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int uart_putc_nb(char c) {
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    uint16_t next = (tx_head + 1) % TX_BUF_SIZE;
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    if (next == tx_tail) return -1;   // full
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    tx_buf[tx_head] = c;
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    tx_head = next;
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    USART1->CR1 |= USART_CR1_TXEIE;
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    return 0;
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}
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int uart_getc_nb(void) {
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    if (rx_head == rx_tail) return -1;
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    uint8_t c = rx_buf[rx_tail];
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    rx_tail = (rx_tail + 1) % RX_BUF_SIZE;
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    return c;
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}

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static uint8_t dma_rx_buf[256];
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static uint8_t dma_tx_buf[256];
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void uart_init_dma(uint32_t baud, uint32_t pclk) {
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    // GPIO + USART1 enable 동일
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    USART1->BRR = (pclk + baud / 2) / baud;
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    USART1->CR1 = USART_CR1_UE | USART_CR1_TE | USART_CR1_RE;
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    USART1->CR3 = USART_CR3_DMAT | USART_CR3_DMAR;
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    RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
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    // RX DMA — Stream 2, Channel 4, USART1_RX, circular
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    DMA2_Stream2->CR = 0;
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    while (DMA2_Stream2->CR & DMA_SxCR_EN);
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    DMA2_Stream2->PAR  = (uint32_t)&USART1->DR;
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    DMA2_Stream2->M0AR = (uint32_t)dma_rx_buf;
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    DMA2_Stream2->NDTR = sizeof(dma_rx_buf);
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    DMA2_Stream2->CR   = (4u << 25)             // channel 4
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                       | DMA_SxCR_CIRC          // circular
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                       | DMA_SxCR_MINC          // memory inc
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                       | DMA_SxCR_EN;
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    // TX DMA — Stream 7, Channel 4, USART1_TX, normal
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    DMA2_Stream7->CR = 0;
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    while (DMA2_Stream7->CR & DMA_SxCR_EN);
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    DMA2_Stream7->PAR  = (uint32_t)&USART1->DR;
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    DMA2_Stream7->CR   = (4u << 25)
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                       | DMA_SxCR_DIR_0          // mem → peripheral
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                       | DMA_SxCR_MINC
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                       | DMA_SxCR_TCIE;
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    NVIC_EnableIRQ(DMA2_Stream7_IRQn);
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}
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void uart_send_dma(const uint8_t *buf, uint16_t len) {
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    while (DMA2_Stream7->CR & DMA_SxCR_EN);   // wait previous
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    DMA2_Stream7->NDTR = len;
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    DMA2_Stream7->M0AR = (uint32_t)buf;
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    DMA2->HIFCR = 0x3F << 22;                 // clear flags
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    DMA2_Stream7->CR |= DMA_SxCR_EN;
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}

1
Polling 모드, 115200 baud (8N1, 87 µs per byte):
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TX: byte | gap 0~5 µs | byte | gap 0~5 µs | ...   ← back-to-back
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Interrupt 모드:
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TX: byte | gap 3~10 µs (ISR overhead) | byte | ...
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DMA 모드:
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TX: byte | gap < 1 µs | byte | ...   ← 거의 perfect back-to-back