AXI 인터페이스 — AXI4·AXI4-Lite·AXI-Stream 비교

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AXI4 (full)    address + 5 channel, burst 1-256, OoO, outstanding
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               메모리·DMA 같은 대용량 transfer
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AXI4-Lite      address + 5 channel, single-beat only, no burst/ID
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               control register (HLS s_axilite)
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AXI-Stream     address 없음, valid/ready/last/keep/user
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               video·audio·sensor·DMA의 data plane

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void accel(int *in, int *out, int n, int mode) {
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#pragma HLS INTERFACE m_axi     port=in   offset=slave bundle=gmem
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#pragma HLS INTERFACE m_axi     port=out  offset=slave bundle=gmem
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#pragma HLS INTERFACE s_axilite port=in   bundle=ctrl
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#pragma HLS INTERFACE s_axilite port=out  bundle=ctrl
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#pragma HLS INTERFACE s_axilite port=n    bundle=ctrl
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#pragma HLS INTERFACE s_axilite port=mode bundle=ctrl
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#pragma HLS INTERFACE s_axilite port=return bundle=ctrl
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    /* ... */
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}

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struct accel_regs {
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    volatile uint32_t ap_ctrl;    /* bit0 START, bit1 DONE, bit2 IDLE */
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    volatile uint32_t ap_gie;
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    volatile uint32_t ier;
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    volatile uint32_t isr;
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    volatile uint32_t in_addr_lo;
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    volatile uint32_t in_addr_hi;
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    /* ... */
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};
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void accel_start(struct accel_regs *r, dma_addr_t in, dma_addr_t out, int n) {
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    r->in_addr_lo  = lower_32_bits(in);
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    r->in_addr_hi  = upper_32_bits(in);
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    r->out_addr_lo = lower_32_bits(out);
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    r->out_addr_hi = upper_32_bits(out);
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    r->n           = n;
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    wmb();
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    r->ap_ctrl     = 0x1;          /* START */
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}

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#pragma HLS INTERFACE m_axi port=buf offset=slave bundle=gmem \
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    max_read_burst_length=256 max_write_burst_length=256

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AXI burst rule:
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- 한 burst는 4 KB boundary를 넘으면 안 된다
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- DMA controller가 자동 split, 손수 master는 직접 split

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/* Pseudo — 4 KB 안에 맞춰 split */
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void split_burst(uint64_t addr, uint32_t len, axi_burst *out, int *nb) {
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    int n = 0;
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    while (len) {
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        uint32_t to_boundary = 4096 - (addr & 0xFFF);
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        uint32_t chunk = min(len, to_boundary);
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        out[n++] = (axi_burst){ addr, chunk };
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        addr += chunk;
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        len  -= chunk;
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    }
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    *nb = n;
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}

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#include <hls_stream.h>
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#include <ap_axi_sdata.h>
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typedef ap_axiu<32, 1, 1, 1> pkt_t;     /* 32-bit data + side-band */
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void parser(hls::stream<pkt_t> &in, hls::stream<pkt_t> &out) {
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#pragma HLS INTERFACE axis port=in
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#pragma HLS INTERFACE axis port=out
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#pragma HLS INTERFACE s_axilite port=return bundle=ctrl
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    pkt_t p;
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    do {
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#pragma HLS PIPELINE II=1
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        p = in.read();
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        p.data ^= 0xCAFEBABE;
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        out.write(p);
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    } while (!p.last);
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}

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Master가 응답 받기 전 새 요청 발사 가능
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Time:   AR0  AR1  AR2  AR3
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                       R0   R1   R2   R3
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Outstanding 4 = 동시 미응답 4개

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#pragma HLS INTERFACE m_axi port=buf max_read_outstanding=16 \
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                                       max_write_outstanding=16

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Same ID에 다른 slave:
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  AR(id=0) → slave A (빠름)
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  AR(id=0) → slave B (느림)
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  → slave B 응답이 늦으면 같은 ID FIFO 순서 때문에 A 응답도 대기
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  → deadlock 가능

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/* AR(id = slave_id | sequence) */
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issue_read(0x10 | seq, slave_A_addr);
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issue_read(0x20 | seq, slave_B_addr);   /* OoO 가능 */

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/* Vivado Block Design에서 ARQOS/AWQOS 설정 */
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/* AXI Interconnect의 register로 master별 priority 변경 */
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#define QOS_CRITICAL  15
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#define QOS_HIGH      10
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#define QOS_NORMAL    5
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set_qos(axi_master_camera_id, QOS_CRITICAL);   /* frame drop 금지 */
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set_qos(axi_master_cpu_id,    QOS_HIGH);
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set_qos(axi_master_dma_id,    QOS_NORMAL);

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#pragma HLS INTERFACE m_axi port=data max_read_outstanding=1

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/* Raw AXI master에서 */
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issue_burst(addr=0x0FF0, len=64);   /* 0x0FF0 ~ 0x10EF, 4KB boundary 침범 */

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#pragma HLS INTERFACE s_axilite port=buffer bundle=ctrl

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pkt.data = sample;
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out.write(pkt);                /* last 안 설정 */

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CPU가 share하는 영역인데 HP로 접근하면 cache flush가 매번 필요