Zynq PS-PL 통신 — GP·HP·ACP 인터페이스 선택

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PS → PL (PS가 master, PL이 slave):
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  M_AXI_GP0, GP1                — General Purpose, 32-bit, 250 MHz
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                                  → PL의 control register access
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PL → PS (PL이 master, PS가 slave):
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  S_AXI_GP0, GP1                — 32-bit, 일반 access
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  S_AXI_HP0..HP3                — High Performance, 64-bit, ~600 MB/s 각
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                                  → DDR 직접 access (cache bypass)
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  S_AXI_ACP                     — Accelerator Coherency Port, 64-bit
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                                  → L2 cache coherent

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// PL 측 AXI-Lite slave (M_AXI_GP의 target)
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module ctrl_regs (
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    input  wire        s_aclk,
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    input  wire        s_aresetn,
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    // ... AXI-Lite slave signals
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    output reg  [31:0] cmd,
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    output reg  [31:0] args[0:7],
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    input  wire [31:0] status,
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    input  wire [31:0] res[0:7]
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);

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volatile uint32_t *regs = (uint32_t*)0x43C00000;   // BAR base
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regs[0] = OP_PROCESS;          // cmd
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regs[1] = buf_addr;
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regs[2] = buf_len;

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S_AXI_HP path:
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  PL AXI master → HP port → DDR controller → DDR
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throughput: 64-bit × 150 MHz × 4 port = ~4.8 GB/s 이론값

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// PS 측에서 buffer 준비
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uint8_t *buf = aligned_alloc(64, SIZE);
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// cache 일관성 위해 *PS write 후 flush*
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__clean_dcache_area_poc(buf, SIZE);
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// PL에 buf physical addr 전달
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regs[0] = OP_DMA;
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regs[1] = virt_to_phys(buf);
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regs[2] = SIZE;
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// PL이 HP로 DDR에서 read
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// 완료 IRQ 받음
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// 결과는 *PL이 DDR에 write*. PS는 cache invalidate 후 read.
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__invalidate_dcache_area_poc(buf, SIZE);
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process(buf);

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S_AXI_ACP path:
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  PL → ACP port → L2 cache (snoop) → DDR (miss 시)
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throughput: HP보다 *낮음* (~400 MB/s)
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latency:    HP보다 *낮음* (cache hit 시)

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// PS 측 — cache flush 필요 없음
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uint8_t *buf = aligned_alloc(64, SIZE);
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prepare(buf);
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regs[0] = OP_ACP_DMA;
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regs[1] = virt_to_phys(buf);
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regs[2] = SIZE;
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// PL이 ACP로 read — L2 cache에서 가져옴
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// PL이 ACP로 write — L2 cache에 쓰임 (snoop)
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// PS가 buf를 다시 읽으면 자동 coherent
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process(buf);

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module mbox_lite #(
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    parameter ADDR_W = 8
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)(
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    input  wire        clk,
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    input  wire        rstn,
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    // AXI Lite slave
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    input  wire [ADDR_W-1:0] s_awaddr,
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    input  wire        s_awvalid,
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    output wire        s_awready,
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    input  wire [31:0] s_wdata,
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    input  wire [3:0]  s_wstrb,
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    input  wire        s_wvalid,
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    output wire        s_wready,
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    output wire [1:0]  s_bresp,
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    output wire        s_bvalid,
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    input  wire        s_bready,
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    input  wire [ADDR_W-1:0] s_araddr,
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    input  wire        s_arvalid,
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    output wire        s_arready,
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    output wire [31:0] s_rdata,
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    output wire [1:0]  s_rresp,
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    output wire        s_rvalid,
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    input  wire        s_rready,
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    // User signal
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    output reg  [31:0] cmd,
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    output reg  [31:0] doorbell,
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    input  wire [31:0] status
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);
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    // ... 매우 길어짐. Vivado IP Wizard가 자동 생성 가능
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endmodule

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module dma_engine (
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    input  wire        clk,
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    input  wire        rstn,
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    // AXI master
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    output reg  [31:0] m_araddr,
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    output reg  [7:0]  m_arlen,        // burst length
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    output reg  [2:0]  m_arsize,
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    output reg  [1:0]  m_arburst,      // INCR / WRAP
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    output reg         m_arvalid,
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    input  wire        m_arready,
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    input  wire [63:0] m_rdata,
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    input  wire        m_rvalid,
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    output reg         m_rready,
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    input  wire        m_rlast,
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    // Control
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    input  wire        start,
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    input  wire [31:0] src_addr,
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    input  wire [31:0] len_bytes
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);
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    // burst read state machine
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endmodule

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int fd = open("/dev/mem", O_RDWR | O_SYNC);
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volatile uint32_t *regs = mmap(NULL, 0x1000, PROT_READ | PROT_WRITE,
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                                MAP_SHARED, fd, 0x43C00000);
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regs[0] = 0x1234;

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int fd = open("/dev/uio0", O_RDWR);
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volatile uint32_t *regs = mmap(NULL, 0x1000, PROT_READ | PROT_WRITE,
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                                MAP_SHARED, fd, 0);
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regs[0] = OP_START;
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uint32_t irq_count;
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read(fd, &irq_count, 4);    /* wait IRQ */

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my_accel@43c00000 {
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    compatible = "generic-uio";
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    reg = <0x43c00000 0x1000>;
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    interrupt-parent = <&intc>;
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    interrupts = <0 29 4>;
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};

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// CMA-allocated coherent buffer
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void *buf = dma_alloc_coherent(dev, SIZE, &dma_handle, GFP_KERNEL);
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// dma_handle은 physical addr — PL에 전달

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dma_read_to(buf, SIZE);    /* PL이 buf 채움 */
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process(buf);              /* PS가 옛 cache 값 봄 */

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// 1 byte씩 100번 write → 100 transaction
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// 32-byte burst 1번 = 25 cycle, 100배 차이

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1 MB을 ACP로 read → L2 cache (256 KB) 전체 오염 → PS performance 폭락

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for (int i = 0; i < 1024; i++) regs[i] = data[i];
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/* → MMIO 1024번, 수십 ms */

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HP0: camera DMA
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HP1: network packet
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HP2: video encoder
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HP3: audio
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→ DDR bandwidth 한계로 *serialize* + jitter 증가