SPI 드라이버 구현 — Master·Slave·CRC·DMA

1
SPI clock = PCLK / 2^(BR + 1)
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3
PCLK2 = 84 MHz, BR = 2 → 84 / 8 = 10.5 MHz

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uint8_t spi_xfer(uint8_t tx) {
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    while (!(SPI1->SR & SPI_SR_TXE));
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    SPI1->DR = tx;
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    while (!(SPI1->SR & SPI_SR_RXNE));
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    return SPI1->DR;
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}
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// 사용
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uint8_t rx = spi_xfer(0xFF);   // read only — TX는 don't care
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spi_xfer(0xA5);                // write only — RX는 버림

1
void spi_init_master(uint32_t div) {
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    RCC->APB2ENR |= RCC_APB2ENR_SPI1EN;
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    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
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    // PA5 SCK, PA6 MISO, PA7 MOSI (AF5)
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    gpio_init(GPIOA, 5, &(gpio_config_t){.mode=GPIO_MODE_AF, .speed=GPIO_SPEED_VH, .af=5});
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    gpio_init(GPIOA, 6, &(gpio_config_t){.mode=GPIO_MODE_AF, .speed=GPIO_SPEED_VH, .af=5, .pull=GPIO_PULL_UP});
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    gpio_init(GPIOA, 7, &(gpio_config_t){.mode=GPIO_MODE_AF, .speed=GPIO_SPEED_VH, .af=5});
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    // CS는 GPIO로 별도 제어 — PA4 (active-low)
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    gpio_init(GPIOA, 4, &(gpio_config_t){.mode=GPIO_MODE_OUTPUT, .speed=GPIO_SPEED_HIGH});
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    GPIOA->BSRR = (1u << 4);   // CS high (deselect)
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    SPI1->CR1 = SPI_CR1_MSTR              // master
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              | (div << 3)                // BR
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              | SPI_CR1_SSM | SPI_CR1_SSI // software NSS, NSS held high
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              | SPI_CR1_SPE;              // enable
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                                          // CPOL=0, CPHA=0, 8-bit, MSB-first
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}

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static inline void cs_low(void)  { GPIOA->BSRR = (1u << (4 + 16)); }
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static inline void cs_high(void) { GPIOA->BSRR = (1u << 4); }
3

4
uint8_t spi_xfer8(uint8_t tx) {
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    while (!(SPI1->SR & SPI_SR_TXE));
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    *((volatile uint8_t *)&SPI1->DR) = tx;    // 8-bit access
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    while (!(SPI1->SR & SPI_SR_RXNE));
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    return *((volatile uint8_t *)&SPI1->DR);
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}
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void spi_write(const uint8_t *buf, size_t n) {
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    cs_low();
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    for (size_t i = 0; i < n; i++) spi_xfer8(buf[i]);
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    while (SPI1->SR & SPI_SR_BSY);   // wait last bit out
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    cs_high();
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}
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void spi_read(uint8_t *buf, size_t n) {
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    cs_low();
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    for (size_t i = 0; i < n; i++) buf[i] = spi_xfer8(0xFF);
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    while (SPI1->SR & SPI_SR_BSY);
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    cs_high();
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}

1
void spi_init_dma(void) {
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    // SPI1 RX = DMA2 Stream 0/2, Channel 3
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    // SPI1 TX = DMA2 Stream 3/5, Channel 3
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    RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN;
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    // RX
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    DMA2_Stream0->PAR = (uint32_t)&SPI1->DR;
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    DMA2_Stream0->CR  = (3u << 25)
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                      | DMA_SxCR_MINC
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                      | DMA_SxCR_TCIE;
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    // TX
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    DMA2_Stream3->PAR = (uint32_t)&SPI1->DR;
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    DMA2_Stream3->CR  = (3u << 25)
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                      | DMA_SxCR_DIR_0
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                      | DMA_SxCR_MINC
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                      | DMA_SxCR_TCIE;
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    SPI1->CR2 |= SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN;
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    NVIC_EnableIRQ(DMA2_Stream0_IRQn);
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}
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volatile int spi_dma_done;
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void spi_xfer_dma(const uint8_t *tx, uint8_t *rx, size_t n) {
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    spi_dma_done = 0;
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    cs_low();
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    DMA2_Stream0->M0AR = (uint32_t)rx;
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    DMA2_Stream0->NDTR = n;
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    DMA2_Stream0->CR  |= DMA_SxCR_EN;
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    DMA2_Stream3->M0AR = (uint32_t)tx;
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    DMA2_Stream3->NDTR = n;
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    DMA2_Stream3->CR  |= DMA_SxCR_EN;
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    while (!spi_dma_done);
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    while (SPI1->SR & SPI_SR_BSY);
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    cs_high();
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}
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void DMA2_Stream0_IRQHandler(void) {
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    DMA2->LIFCR = DMA_LIFCR_CTCIF0;
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    spi_dma_done = 1;
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}

1
typedef struct {
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    GPIO_TypeDef *cs_port;
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    uint16_t      cs_pin;
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    uint8_t       div;        // baud divider per slave
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    uint8_t       mode;       // CPOL/CPHA
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} spi_slave_t;
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static spi_slave_t flash = {GPIOA, 4, 0, 0};
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static spi_slave_t adc   = {GPIOA, 3, 2, 1};
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void spi_select(const spi_slave_t *s) {
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    SPI1->CR1 &= ~SPI_CR1_SPE;
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    SPI1->CR1 = (SPI1->CR1 & ~((7u << 3) | SPI_CR1_CPOL | SPI_CR1_CPHA))
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              | (s->div << 3)
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              | ((s->mode & 2) ? SPI_CR1_CPOL : 0)
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              | ((s->mode & 1) ? SPI_CR1_CPHA : 0)
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              | SPI_CR1_SPE;
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    s->cs_port->BSRR = (1u << (s->cs_pin + 16));   // CS low
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}
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void spi_deselect(const spi_slave_t *s) {
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    while (SPI1->SR & SPI_SR_BSY);
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    s->cs_port->BSRR = (1u << s->cs_pin);   // CS high
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}