Atomic Operation 비용 분석 — Fence·Cache Line·Contention

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load
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  relaxed       LDR
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  acquire       LDAR        (one-way acquire fence)
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  seq_cst       LDAR
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store
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  relaxed       STR
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  release       STLR        (one-way release fence)
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  seq_cst       STLR + DMB ISH
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fetch_add
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  relaxed       LDXR/STXR loop (ARMv8.0) or LDADD (ARMv8.1 LSE)
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  seq_cst       LDAXR/STLXR loop or LDADDAL

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std::atomic<bool> ready{false};
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std::atomic<int>  data{0};
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/* producer */
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data.store(42, std::memory_order_relaxed);
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ready.store(true, std::memory_order_release);
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/* consumer */
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while (!ready.load(std::memory_order_acquire));
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int v = data.load(std::memory_order_relaxed);
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/* v == 42 보장 */

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std::atomic<long> counter;
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void inc(void) { counter.fetch_add(1, std::memory_order_relaxed); }

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1:  ldxr    x0, [x1]
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    add     x0, x0, #1
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    stxr    w2, x0, [x1]
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    cbnz    w2, 1b      // retry on failure

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mov     x0, #1
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ldadd   x0, xzr, [x1]    // single atomic

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/* 나쁨 — atomic load만 hot loop */
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while (flag.load(std::memory_order_acquire)) {
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    /* 매 iteration LDAR — cache line invalidate */
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}
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/* 좋음 — yield/pause로 backoff */
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while (flag.load(std::memory_order_relaxed)) {
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    __asm__ volatile("yield" ::: "memory");
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}
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if (flag.load(std::memory_order_acquire)) { ... }

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struct alignas(64) shard {
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    std::atomic<long> v;
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};
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shard counters[N_CPU];
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void inc(int cpu) {
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    counters[cpu].v.fetch_add(1, std::memory_order_relaxed);
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}
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long total(void) {
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    long s = 0;
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    for (int i = 0; i < N_CPU; i++)
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        s += counters[i].v.load(std::memory_order_relaxed);
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    return s;
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}

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/* OK — counter는 monotonic increment만, 순서 무관 */
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total.fetch_add(1, std::memory_order_relaxed);
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/* NOK — flag 후 data 읽기는 release/acquire 필요 */
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ready.store(true, std::memory_order_relaxed);    /* 다른 thread가 data를 못 봄 */

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std::atomic<int> a;       // is_always_lock_free == true
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std::atomic<int64_t> b;   // 32-bit arch에서 false (mutex 내장)
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std::atomic<__int128> c;  // 대부분 false (DCAS)

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연산 (Cortex-A72, no contention)
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LDR / STR                  1 cycle
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LDAR (acquire load)        2 cycle
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STLR (release store)       2 cycle
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LDAXR/STLXR loop           4~6 cycle
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LDADD (LSE)                3 cycle
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DMB ISH                    10~20 cycle

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contention 시 (8 thread, 같은 변수)
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LL/SC fetch_add            >200 cycle/op
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LSE   fetch_add            ~50 cycle/op
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mutex lock/unlock          ~150 ns
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per-CPU counter            10 cycle/op

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spin loop 영향 (다른 코어에서 store)
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hot LDAR 없음              store latency 4 cycle
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hot LDAR 있음              store latency 60+ cycle
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yield로 backoff            store latency 8 cycle

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std::atomic<int> a;
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a.fetch_add(1);    /* default = seq_cst — 가장 비쌈 */

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volatile int flag;    /* 동기화 안 됨 — UB */

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std::atomic<int64_t> x;   /* mutex 사용 — lock-free 아님 */

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while (locked.load());   /* hot LDR — 시스템 전반 영향 */

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flag.store(true);    /* default seq_cst */
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/* 코드 다 짜고 나서 "relaxed로 되나?" 고민 — 위험 */