Vitis HLS 분석 — Pragma·Pipeline II·Dataflow 실전 감각

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#include <ap_int.h>
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#include <hls_stream.h>
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#define TAPS 32
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void fir(hls::stream<int16_t> &in,
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         hls::stream<int16_t> &out,
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         const int16_t coeff[TAPS]) {
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#pragma HLS INTERFACE axis      port=in
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#pragma HLS INTERFACE axis      port=out
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#pragma HLS INTERFACE s_axilite port=coeff bundle=ctrl
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#pragma HLS INTERFACE s_axilite port=return bundle=ctrl
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    static int16_t shift[TAPS] = {0};
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#pragma HLS ARRAY_PARTITION variable=shift complete
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    int16_t sample = in.read();
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    SHIFT: for (int i = TAPS - 1; i > 0; i--) {
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#pragma HLS UNROLL
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        shift[i] = shift[i - 1];
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    }
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    shift[0] = sample;
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    int32_t acc = 0;
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    MAC: for (int i = 0; i < TAPS; i++) {
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#pragma HLS UNROLL
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        acc += (int32_t)shift[i] * (int32_t)coeff[i];
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    }
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    out.write((int16_t)(acc >> 15));
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}

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void fir_mm(int16_t *in, int16_t *out, int n,
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            const int16_t coeff[TAPS]) {
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#pragma HLS INTERFACE m_axi      port=in    offset=slave bundle=gmem0 \
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                                  max_read_burst_length=256
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#pragma HLS INTERFACE m_axi      port=out   offset=slave bundle=gmem1 \
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                                  max_write_burst_length=256
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#pragma HLS INTERFACE s_axilite  port=n     bundle=ctrl
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#pragma HLS INTERFACE s_axilite  port=coeff bundle=ctrl
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#pragma HLS INTERFACE s_axilite  port=return bundle=ctrl
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    static int16_t shift[TAPS] = {0};
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#pragma HLS ARRAY_PARTITION variable=shift complete
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    for (int n_i = 0; n_i < n; n_i++) {
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#pragma HLS PIPELINE II=1
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        /* ... 위와 동일 logic ... */
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    }
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}

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void image_pipe(hls::stream<pixel> &in,
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                hls::stream<pixel> &out) {
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#pragma HLS DATAFLOW
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    hls::stream<pixel> s1, s2;
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#pragma HLS STREAM variable=s1 depth=32
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#pragma HLS STREAM variable=s2 depth=32
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    blur     (in,  s1);
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    sharpen  (s1,  s2);
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    threshold(s2, out);
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}

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/* Naive — recurrence */
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for (int i = 1; i < N; i++) {
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#pragma HLS PIPELINE II=1
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    a[i] = a[i - 1] + b[i];       /* II=2~3로 떨어짐 */
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}
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/* Tree reduction */
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int partial[4] = {0};
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for (int i = 0; i < N; i++) {
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#pragma HLS PIPELINE II=1
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    partial[i & 3] += b[i];        /* 4-way 누적 */
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}
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int total = partial[0] + partial[1] + partial[2] + partial[3];

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ap_uint<10> coord_x;            /* 0..1023 */
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ap_int<24>  sample;              /* 24-bit ADC */
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ap_fixed<16, 1> gain;            /* 1.15 fixed-point */

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int main() {
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    hls::stream<int16_t> in, out;
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    int16_t coeff[TAPS] = { ... };
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    for (int i = 0; i < 1024; i++) in.write(test[i]);
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    fir(in, out, coeff);
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    for (int i = 0; i < 1024; i++) assert(out.read() == expected[i]);
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    return 0;
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}

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+ Latency:
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    * Loop:
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      |Loop Name |min |max |Iter Latency |Init Interval |Trip|
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      |MAC       |  3 |  3 |           3 |            1 |  32|
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+ Utilization Estimates:
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    BRAM_18K: 2     DSP48E: 32     FF: 1812     LUT: 2154

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void foo(int *a, int *b, int n) {
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    for (int i = 0; i < n; i++) {
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#pragma HLS PIPELINE II=1
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        a[i] = b[i] + 1;          /* a와 b가 겹칠 수 있다고 가정 */
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    }
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}

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int *buf = new int[N];            /* 합성 안 됨 */
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recursive_fn(n);                   /* 안 됨 */
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printf(...);                       /* 합성 단계에서 무시 */

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float gain = 1.5f;
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out[i] = in[i] * gain;

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int buf[1024];
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for (...) {
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#pragma HLS UNROLL factor=4
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    sum += buf[i];                 /* BRAM 단일 port → 직렬화 */
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}

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#pragma HLS DATAFLOW
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    stage1(in, mid);              /* mid는 array */
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    stage2(mid, out);

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fir(in, out, host_coeff);          /* 매 frame coeff DMA */